1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device and, more particularly, to a circuit and method for generating an output control signal in a synchronous semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices used as main memories in a computer system perform their role by inputting/outputting data to/from memory cells. The speeds of the data input/output operations of the semiconductor memory devices are important factors in determining the operating speed of the computer system. To improve the operating speed of the semiconductor memory devices, a synchronous dynamic random access memory (SDRAM, Synchronous DRAM) device in which internal circuits are controlled in synchronization with a generated clock signal from the computer system has been used.
Generally, the SDRAM uses a Column Address Strobe (CAS) latency function to increase an operation frequency. The CAS latency is defined as a time delay that is needed from the time of application of a read command before an outputted data signal can be presumed to be valid. This time delay can be represented as an integer number of cycles of a generated external clock signal with the read command being synchronized with that external clock.
Since the actual time delay (tAA) is constant for a given SDRAM, the CAS latency may be changed as a function of the operation frequency of the device. For example, if the tAA is 15 ns and the operation frequency is 200 MHz, the CAS latency becomes 3 because the period of the external clock signal is 5 ns. If the tAA is 15 ns and the operation frequency is 333 MHz, the CAS latency becomes 5 because the period of the external clock signal is 3 ns.
FIG. 1 illustrates a conventional output control signal generating circuit of a synchronous semiconductor memory device. Referring to FIG. 1, an output control signal generating circuit 100 includes a multiplexer 110 and a shift register 120.
The shift register 120 shifts a read master signal (RM) sequentially in response to an output control clock signal (PCLKDQ). PCLKD, which represents a signal generated through a delay locked-loop circuit (DLL, not shown) included in the synchronous semiconductor memory device, controls a data signal to be outputted in synchronization with the external clock signal (not shown). Typically, PCLKD is generated before the generation of the corresponding external clock signal in order to satisfy a condition where tAC (output data access time from external clock) is zero. A read master signal (RM), as a signal indicating the output interval of the data, is synchronized with an internal clock signal (not shown), which is the external clock signal delayed by a predetermined time.
The multiplexer 110 selectively outputs one of the output signals (RM_S1A, RM_S2A, RM_S3A, RM_S4A) of the shift register 120 as an output control signal (LATENCY) in response to CAS latency signals (CL2, CL3, CL4, CL5, respectively) indicating the activation of a CAS latency. The output control signal (LATENCY) is applied to an output buffer (not shown) included in the synchronous semiconductor memory device to cause the data to be outputted (i.e. activated) during an appropriate data output time interval.
FIG. 2 illustrates a timing diagram of the operation of the output control signal generating circuit shown in FIG. 1 when the CAS latency is 3. An internal clock signal (PCLK), which is generated from an external clock signal (ECLK) having a period TCC1, is delayed to time T1 from the rising edge of external clock (ECLK). An output control clock signal (PCLKDQ) is set such that it is generated earlier (T2 time) than the rising edge of a portion (ECLK1) of the external clock (ECLK).
A significant disadvantage of the circuit shown in FIG. 1 is that since the output control clock signal (PCLKDQ) typically leads the read master signal (RM), which is synchronized to the phase of the internal clock signal (PCLK), invalid read master signal (RM) may be sampled in the first cycle shown in FIG. 2 for an exemplary CAS latency of 3. To sample valid read master signal (RM), the output control clock signal (PCLKDQ) needs to be delayed by a time TD as shown in FIG. 2. The delay time (TD) and a resulting delayed output control clock signal (PCLKDQ_D) are shown in FIG. 2, and can be represented by the numerical expression,(TCC1−T2)+TD>T1, TD>T1−(TCC1−T2). 
Generally, in a device using the DLL, the output control clock signal (PCLKDQ) is generated to occur earlier than the corresponding external clock signal in order to satisfy the TAC=0 condition, and the early activation time of PCLKDQ is set to be constant (i.e., independent of the operating frequency.) Thus, as the frequency of the external clock signal (ECLK) increases (that is, as the period (TCC1) of ECLK decreases), the delay time (TD) needs to be increased. Thus, since the conventional synchronization circuits have no provisions for variable synchronization delays, invalid output signals from output control signal generating circuit 100 may be generated at higher clock frequencies, thereby providing invalid output data from the SDRAM.